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hpola3
New Contributor
New Contributor50/60Hz Digital PLL
We want to implement a digital 50/60Hz PLL for synchronisation purpose. We want to replace an old HEF4046B IC. Is it possible to design a 50/60Hz with FPGA/CPLD (MAX10 family i.e)? do you have any ...
hpola3New Contributor
New ContributorHi Rahus,
In Max10 internal PLLs minimum frequency range is in MHz range.
I need a PLL for 50/60Hz application (grid frequency lock). Also PLLs has a filter which adjust its slew rate and speed.
Do you think is it possible with Max10 family? Do you have an IP of reference design for such application?
