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JKobl1's avatar
JKobl1
Icon for New Contributor rankNew Contributor
6 years ago
Solved

4-bit Synchronous JK flip flop Counter Erratic

See attached image. Built a simple 4-bit synchronous counter in Quartus Prime using 7473 chips. This works erratically on DE10-Lite board with standard MAX 10 FPGA. Expect synchronous counting, ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

You should try simulating the design with the included ModelSim-Intel FPGA starter edition software. Also, you should add a .sdc file. Without that, there's no guarantee that the Fitter will place and route your design in such a way to meet timing.

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