Forum Discussion
Calvin9
New Contributor
6 years agoHi,
Thanks for the reply!
The precise term mentioned is "dual slot interface" in arria 10 EMIF user guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
1. What the design requires is having two different interfaces to access ddr simultaneously. As mentioned in your reply, is it possible to have two memory controller IP's instantiated in the top level?
2. And when there are two DIMMS of 4GB each, which makes up for a toatal memory of 8GB, each interface (in case two memory controllers are used) can access entire 8GB memory?
3. Also, could you please let me know what single dual DIMM interface (mentioned in your reply) is?