Forum Discussion
BoonT_Intel
Frequent Contributor
6 years agoAlso, from which documentation you notice dual channel? I don't think Intel FPGA EMIF claim about "dual channel" term anywhere. And what sstrell asking is correct. Are you mean dual rank? or may you are asking 2 DDR4 interface which require you to instantiate the IP 2 times from your top level. when there are dual DIMM, there are few possibility like single dual DIMM interface, 2 interface with 2 DIMMs.