对于带有FEC应用，要求tx_clkout给tx_coreclkin和rx_coreclkin用。那rxdata的随路时钟是否为tx_clkout？这样的话我们无法保证tx_clkout（referent clk产生）与高速串行时钟恢复的rx_clkout一定无频偏，如果内部fifo出现空满丢数据怎么办？

Hi,

As I understand it, you have some inquiries related to the tx_clkout and rx_clkout. To ensure we are on the same page, would you mind to share with me your Native PHY instance .ip or .qsys file so that I can have further understanding on your configuration. This would be helpful for me to further comment on your inquiry.

Thank you.