客户使用开发板自带的BTS文件，加载DDR3例子后，报DDR3校准错

HI,

By the way, don't use signal_tap to measure DDR3 refclk pin. This is hard circuit pin. SIgnal_tap can only be used to measure FPGA soft logic design insides FPGA core but not FPGA hard circuitry

• A better approach is to use oscilloscope probe to measure on board clock pin to check whether there is clock present or not and whether the clock frequency is correct or not

Anyway, thanks for isolating down the issue to no clock output from on board clock generator chip U64.

There 3 possibility that I can think of

1. Customer is using prototype C10 GX board. There is no clock output from U64 as it's not program correctly on these prototype board

• C10 GX prototype board serial number is within 0000001-0000030. Can you check what's the serial number of your customer board ?
  • If confirmed it's prototype board then pls follow attached guideline to program U64 everytime user power cycle C10 GX board

1. Customer is using production C10 GX board but somehow corrupted U64 programming

• You can also follow attached guideline to program back U64 chip

1. Customer is using production C10 GX board but U64 chip is defective

• Pls follow attached guideline to program back U64 chip, after that pls probe on the board on U64 output to confirm there is really no correct clock toggling
  • Once confirmed this is really defective C10 GX board, then I will transfer this case to another Intel support agent to help you process the board warranty claim

Thanks.

Regards,

dlim