Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHI,
I would like to clarify the problem statement here.
- Are you trying to report an issue with a defective Intel FPGA dev kit board here or are we dealing with customer own DDR3 design calibration failure issue here ?
- If this is related to dev kit issue
- May I know which Intel FPGA dev kit board that we are talking about here ?
- Pls provide the screenshot of the error saw on customer dev kit board
- Has customer check to ensure all switches on the dev kit board is set to factory default setting as per the user manual doc ?
- Is customer using original BTS from dev kit board download website and pair with the recommended Quartus version ?
If this is new dev kit board issue and once we confirmed the board is defective,
- then Intel will perform warranty check
- customer can request for replacement claim if it's within warranty period else no replacement if warranty already expired
Thanks.
Regards,
dlim
EZhan
New Contributor
6 years ago是一块C10 GX devkit,采用官方提供的BTS测试,并且用EMIF带的design example测试了都是不行的,表现为DDR3 IP 的参考时钟不对,refclk_emif_p就是ddr3参考时钟,按照要求应该是21.186M,应该有U64的outclk4提供,但signaltap抓取全为1,其他由U64提供的时钟也都不正确,并且我尝试用clock controller 配置或disable这几个时钟都没有反应,signaltap的结果一致