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DAVID455912142's avatar
DAVID455912142
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1 year ago

Why does my cyclone V GX pcie fail to establish communication when the temperature is low?

We are establishing connections and communication between the PCIe IP core of CYCLONE V GX FPGA and the CPU daughter card. The chip model is 5CGXF7C6F23I. We conducted experiments by heating the FPG...
VenT_Altera's avatar
VenT_Altera
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1 year ago

Hi DAVID455912142,


Regarding the 7 pieces that needed to be powered on and work for 3-4 minutes to heat up, were they originally placed at room temperature?


Could you please check the following items?

1. Can the FPGA be configured using JTAG?

2. Can the flash be programmed using JTAG?

3. Can FPGA be loaded from flash using AS configuration - regardless of the temperature condition. Hot/Cold/Room

4. Can you see the CONF_DONE signal turned HIGH after the AS configuration? (flash uploaded its contents into FPGA).

5. Can you share whether the timing closure of the project has violation or not?


Thanks.

Best Regards,

Ven


DAVID455912142's avatar
DAVID455912142
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1 year ago

Hi ven

1. YES,I Can the FPGA be configured using JTAG!

2. YES,Can the flash be programmed using JTAG!

3.YES, FPGA be loaded from flash using AS configuration - regardless of the temperature condition!

4.I can see the CONF_DONE signal turned HIGH after the AS configuration.

5.Please refer to the attachment for compilation information.

6.Test record are some test records of hardware.

Thanks.

Best Regards,

david