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BDE00's avatar
BDE00
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6 years ago

Unable to read frequency in Cycloen10LP IOs from design circuit, same is working fine when signal generator is using.

One of my project, i am using Cyclone 10LP, due to obsolete of cyclone first gen, i am using 10LP for reading frequency, Problem is : I am not able to read frequency when IO is connected to proven c...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Balakrishna,

Apologize that we cannot do power-on delay in FPGA. Perhaps that need to be done on board level.

Thank You.

  • BDE00's avatar
    BDE00
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you.!

    In Board level their is a 5 to 7 Sec input power-on Delay,

    Is this timing is sufficient to configure from EEPROM(EPCQ4ASI8N)?

    is their any option to figure out the timing required/reduce the time for FPGA ready? and start the reading the input.