Unable to compile the vector add usm program for any FPGA hardware

Hey,

sadly you did just include an screenshot of the .e file, but in the .o file should be the exact error message. If the error is caused by the board-package, take a look at this post:

https://community.intel.com/t5/Intel-DevCloud/Unable-to-get-output-from-oneAPI-Base-Toolkit-s-vector-add/m-p/1422224/highlight/true#M6328

Thank you for the reply.

I looked into the link provided and added the BSP flag for stratix usm. I was able to compile the sample but I am not able to run it on an FPGA. Below are the steps I followed while trying to compile and run the code. Could you let me know where I went wrong.

1) created a compile_and_run.sh file with the following content

#!/bin/bash
source /opt/intel/inteloneapi/setvars.sh --force

cd oneAPI-samples/DirectProgramming/DPC++/DenseLinearAlgebra/vector-add/src

echo STARTING COMPILATION
dpcpp -fintelfpga -Xshardware -Xsboard=/opt/intel/oneapi/intel_s10sx_pac:pac_s10_usm vector-add-usm.cpp -o vector_usm.fpga
echo COMPILATION DONE

echo STARTING TO RUN ON FPGA HARDWARE
./vector_usm.fpga
echo RUN COMPLETE

2) submitted the job to a node containing fpga_compile property (qsub -l node=1:fpga_compile:ppn=2 -d . compile_and_run.sh)

3) The resulting output and error files were generated (screenshots attached)

4) While I tried to run the stratix code on a node having 'fpga_compile' I could not run it. So I opened an Interactive session with a node having 'fpga-runtime' and 'stratix10' as properties and ran the code (./..../vector_usm.fpga). The following was the result :

Running on device: Intel(R) FPGA Emulation Device
Vector size: 10000
An exception is caught while adding two vectors.
terminate called after throwing an instance of 'cl::sycl::runtime_error'
what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY)
Aborted

For some reason it is not able to select the FPGA hardware. Is there a particular node having usm supported FPGA ?

Hey,

first of: You ca not run the fpga-executables on the fpga_compile-nodes. It is therefore necessary to use the runtime-nodes (As you did in the later steps).

On the stratix-node, you will probably need to initialize the board using the usm-bsp:

aocl initialize acl0 pac_s10_usm

Before this, sycl-ls could returns something like this:

uxxxxx@s001-n142:~/$ sycl-ls
[opencl:cpu:0] Intel(R) OpenCL, Intel(R) Xeon(R) Platinum 8256 CPU @ 3.80GHz 3.0 [2022.14.7.0.30_160000]
[opencl:acc:1] Intel(R) FPGA SDK for OpenCL(TM), pac_s10 : Intel PAC Platform (pac_ee00000) 1.0 [2022.3]
[host:host:0] SYCL host platform, SYCL host device 1.2 [1.2]

After initializing it should return the following:

uxxxxx@s001-n142:~/$ sycl-ls
[opencl:cpu:0] Intel(R) OpenCL, Intel(R) Xeon(R) Platinum 8256 CPU @ 3.80GHz 3.0 [2022.14.7.0.30_160000]
[opencl:acc:1] Intel(R) FPGA SDK for OpenCL(TM), pac_s10_usm : Intel PAC Platform (pac_ee00000) 1.0 [2022.3]
[host:host:0] SYCL host platform, SYCL host device 1.2 [1.2]

Hope this helps,
Christoph

Hi,

i am working on it. pls give me some time. i'll get back to you.

Hi,

https://www.intel.com/content/www/us/en/developer/articles/code-sample/vector-add.html?wapkw=compiling%20the%20sample%20vector%20add%20usm

i think above article will helps you. please go through it. i am also trying from my side to duplicate the issue.

Thanks,

Hi,

any update?

still do you facing that problem?

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