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LHinC1
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6 years ago

Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi everybody , we used Arria 10 FPGA with PHY Lite in our last design. In our new design , we migrate to Stratix 10 and we use PHY Lite to interface DDR4 DRAM. The architecture of Arria 10 PHY Lite i...
LHinC1's avatar
LHinC1
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6 years ago

Hi Aida ,

We have checked all the connections in our design but we do not find any thing wrong yet.

Could we send you part of our codes which involves PHY Lite and have Altera AE help us to take a look ?

Thanks ,

Samson