Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi Samson,

Thanks for checking.

When you migrate the design (from Arria 10 PHY Lite to Stratix 10 PHY Lite), just wonder whether do you make any changes or just migrate the design only? As I know there is a different on bit address mapping between Arria 10 and Stratix 10. As you can see below, for Arria 10 it have 28 bits but for Stratix 10 is 31 bits.

I can see that you are enabling dynamic configuration in the design. Have you try run the reference design ? You may find it useful to run the reference design simulation and see whether the waitrequest signal issue is able to replicate and compare the signal with your custom design. The reference design files can be downloaded from Intel Design Store and restore the design using Intel Quartus Prime Pro Edition software. It is always recommended to use latest version of Quartus software. You can use this reference design as a starting point design and modify as required to suit your design application.

Refer to this Application Note (AN) on the steps to set up and run the simulation reference design --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an888.pdf

Let me know your feedback.

Thanks

Regards,

Aida