New ContributorStratix 10 oneapi: Kernel CLK vs clock 2x
It says we can get 2x core performance as it helps the design to operate at a higher frequency.That is purely a PR claim that holds little real value/meaning in practice; hyperflex just provides a modest improvement in Fmax for routing-congested designs because it makes more registers available to the router. 2x improvement will never happen (at least not without changing the actual code, as well).
The 2x clock that you see in the report is unrelated to hyperflex and is just used for Block RAM double-pumping, which is not actually used by default in Stratix 10 designs anyway and Intel advises against using it for this FPGA family (https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html#jhl1520273455239). Your design will always run at the 1x clock and the build process will automatically make sure it runs at the maximum possible frequency by re-routing multiple times based on the worst-case slack of the design when synthesized with an unrestricted clock frequency. Though If you do force Block RAM double-pumping as outlined in Section 10.3 of the documentation I linked above, then only (and only) the Block RAMs in your design will run at the 2x clock, while everything else will still run at the 1x clock.
