SpurthyNew Contributor2 years agoState Machine File input and output ports. I am using Quartus Prime for generating HDL code from state diagram drawn using state machine file editor, was wondering if the inputs and outputs can be more than 1 bit, as there is no option for se...Show More
ShengN_alteraSuper Contributor2 years agoHi,Let me know if you have any further update or concern?Thanks,Best Regards,Sheng
Recent DiscussionsHLS Compiler 24.1 error - aocl-clang.exe - dll entry point not foundSolvedError faced while executing on Agilex FPGA board....AI Suite System Throughput IssueAgilex 7 I-Series "aocl diagnose acl0" error following OFSHow Do I get the License for HLS?