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ost's avatar
ost
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3 years ago

Simple standalone IP using oneAPI?

I wonder if oneAPI is able to generate a standalone IP block with defined IO ports, just like HLS can do. I have been playing with the oneAPI compiler examples, and it appears like the compiler can just generate full designs on specific supported hardware with an interface to a PC, linking the PC executable and the FPGA functions.

If the compiler is able to do component only, is there an example that does this? I would like to see how to define the IO ports for it. Both scalar and stream ports.

If the compiler is (yet) unable to do this, are there any plans of supporting this?

High-level Design Tools

5 Replies

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    3 years ago

    Hi @ost,


    Thank you for posting in Intel community forum and your interest in oneAPI, hope all is well and apologies for the delayed in response.

    If I understand your question correctly, short answer is yes, we do have a separate compilation flow will allow oneAPI to generate standalone IP block, which is called oneAPI IP Authoring(IPA). More details can be found in the getting started guide link below:

    - https://www.intel.com/content/www/us/en/docs/programmable/749869/22-4/getting-started-with-oneapi-ip-authoring-18311.html


    Readily available example design can be found and compiled in the github link below:

    - https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/experimental/platform_designer


    Hope that clarify.

    Best Wishes

    BB


  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    3 years ago

    Hi @ost,


    Good day, by any chances did you managed to look into the it?

    Just checking in to see if there is any further doubts in regards to this matter


    Best Wishes

    BB


  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    3 years ago

    Hi @ost,


    Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.


    Best Wishes

    BB


  • ost's avatar
    ost
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thanks BB. You example design link looks very interesting. I will dig into it and come back if I meet problems.

  • ost's avatar
    ost
    Icon for New Contributor rankNew Contributor
    3 years ago

    Alright, I got to read the example, and there are several unclear issues to me.

    Yes, it appears like I can attach this adder IP to some memory mapped host interface. I can also export this OutputPipe (sourcecode) class to a mysterious memory mapped agent interface (called add_report_di_0_csr_ring_root_avs), but only drivers and software will (may?) explain how this mapping works out. As a mainly FPGA skilled man, I honestly did not expect a pipe to instantiate as a memory mapped interface.

    There is a lot of mystery in this. Since I (at this time) care less about hooking the IP to a memory mapped host, I would like to know how I can get scalar IO (both in and out), and HLS compatible stream interfaces, also both in and out from oneAPI coding. Keep in mind I want to write code that mainly resolves to II=1, so memory mapping interfaces are not very interesting.

    Also, I am curious to know what is, and how I can control the IRQ sender and exception bus that is generated from the code.

    Can you help? Should I just stay with HLS for what I want to do?

    Best regards,