OneAPi: Iterative read write with swapped memory locations

Hi Yuguen,

Thanks for the reply.
Agree that DDR read should be stall enabled and DDR write should also be stall enabled.
But I want independent DDR read and write clusters for the inner loop since there is no dependency.
It seems like DDR read, Pipe Write, Pipe Read, and DDR write come under the same stall-enabled cluster.

Is there any way to make DDR read and Pipe Write as a separate stall enabled cluster and Pipe read and DDR write to another stall enabled cluster? DDR read shouldn’t stall DDR write

Basically what I want is,
a chunk of data needs to be read (size could be larger than on-chip memory), processed(there is a kernel pipeline), and written back. all these should happen in parallel. on the next iteration, the read and write location should be swapped.

The above code tries to implement the read and write-back of the results in an iterative loop swapping memory locations.
implementing mem read and mem write in the separate kernel doesn't allow swapping as a buffer should be used in one kernel in non-USM designs. when I tried this, the design hangs.

Is there any way to implement this? any suggestions/ advice is highly appreciated

Many Thanks,
Vasan