Forum Discussion

jjb169's avatar
jjb169
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

Hello, I've been working through the Open FPGA Stack (OFS) guides to set up my Agilex 7 I-Series development kit for use with oneAPI. I've worked through prior SystemVerilog issues encountered by sw...
jchecmu's avatar
jchecmu
Icon for New Contributor rankNew Contributor
5 months ago

The board model file is nothing more than the total FPGA resources (ALMs, FFs, DSPs, M20Ks, etc). You can read more about it here oneAPI Accelerator Support Package(ASP) Reference Manual - OFS and look at the existing ones for reference.

I need some time to clean up the repo but will get to it when I can 

For AGIB027R29A1E1VB, the resource counts are:

<alms num="912800"/>

<ffs num="3651200"/> <!-- 4xALMs, since there are 4 FFs per ALM. hyper-regs not counted -->

<dsps num="8528"/><!-- 27-bit elements -->

<rams num="13272"/><!-- M20Ks -->

<mlabs num="45640"/> <!-- half of total labs (10 ALMs each) -->

 

jjb169's avatar
jjb169
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hello,

Thank you for the clarification! Sorry for the delay, I've been running into crashes during compilation that I think are memory related, so I'm currently waiting on a delivery of 128GB RAM.

On one run, however, I did encounter a compilation error as shown below, but I'm thinking it may be due to a mistake I made when modifying the mem_ss.ip as you listed in step 2.

Error (17045): Input port I of I/O input buffer primitive local_mem_wrapper|mem_ss_top|mem_ss_inst|mem_ss|hps_emif|hps_emif|arch|arch_inst|bufs_inst|gen_rzqin.ibuf is not connected. It must be driven by a top-level pin. File: /home/jbick/OFS/OFS_BUILD_ROOT/ofs-agx7-pcie-attach-slim/work_iseries-dk_minimal_fim/ipss/mem/qip/mem_ss/mem_ss/mem_ss_mem_ss_200_rod65uq/synth/ip/mem_ss_mem_ss_200_rod65uq/mem_ss_mem_ss_200_rod65uq_emif_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv Line: 1138

Error: Failed to synthesize partition 

Once my RAM is delivered and installed, I will try the process once more and report the results!

Thanks!
James

  • jchecmu's avatar
    jchecmu
    Icon for New Contributor rankNew Contributor
    4 months ago

    Upon further testing, I found that my solution still has errors. Even though aocl diagnose passes, the default vector add program fails. I am trying to understand the issue before I share more. Thanks

    • jchecmu's avatar
      jchecmu
      Icon for New Contributor rankNew Contributor
      4 months ago

      Hi,

      I can verify that AGIB027R29A1E1VB works with the OFS 2024.1 environment and oneAPI 2024.0 compiler. 

      The AGIB027R29A1E1VB board has 2 on-board 8GB component memory and 2 external DIMM slots. The board comes with a single 16 GB RDIMM module upon purchase. However, OFS was verified using 2x8 GB UDIMMs for the external slots. 

      To get the board to work:

      1. Swap the RDIMM for 2 UDIMMs (you can get the board to work without the external DIMMs, but for such an expensive board you might as well spend another $100. If you are unable to, let me know and I can share the workaround)
      2. If you are using OFS 2024.1 or OFS 2024.2, change the Agilex Device Number following the instructions here: PCIe Attach I-Series (2xR-Tile, F-Tile) - OFS
      3. Following the previous instructions, update the pinout constraints by updating the files 

        $OFS_ROOTDIR/syn/board/iseries-dk/setup/emif_loc.tcl and $OFS_ROOTDIR/syn/board/iseries-dk/setup/top_loc.tcl. I took the constraints from OFS 2024.3

      It turns out that in OFS versions newer than 2024.3, they use the exact same device number AGIB027R29A1E1VB instead of the Early Silicon sample. They also tell you which Micron UDIMMs they used so you can buy the exact same model. Check out the explanation here PCIe Attach I-Series (2xR-Tile, F-Tile) - OFS

      I am working on verifying the board with the OFS 2024.2 environment and oneAPI 2025.0. I am also interested in trying OFS 2024.3 with oneAPI since it uses our exact board, even though oneAPI is only officially supported up to OFS 2024.2. 

      Out of curiosity, do you mind me asking what you are using oneAPI for?

      • jjb169's avatar
        jjb169
        Icon for Occasional Contributor rankOccasional Contributor
        1 month ago

        Hello,

        Apologies for my absence, I've been busy with the end of a semester and creating/defending my PhD proposal.

        Thank you for sharing this information! I'll go ahead and see about swapping out the memory sticks and following your steps to see if I can get them to work as well.

        For clarity, I follow those first two steps you lay out, copy the "emif_loc.tcl" and "top_loc.tcl" from the OFS 2024.3 Github and replace the pre-existing ones, then build the FIM and ASP? Or are the other 10 steps you outlined previously (removing north/south I/O, modifying the board_spec.xml, etc.) still needed?

        We're interested in using oneAPI for acceleration architectures on this FPGA, since oneAPI is (as far as I'm aware) what Altera is using for their HLS toolkit at this time.

        Best,

        James