Forum Discussion

jjb169's avatar
jjb169
Icon for New Contributor rankNew Contributor
4 months ago

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

Hello, I've been working through the Open FPGA Stack (OFS) guides to set up my Agilex 7 I-Series development kit for use with oneAPI. I've worked through prior SystemVerilog issues encountered by sw...
jchecmu's avatar
jchecmu
Icon for New Contributor rankNew Contributor
1 month ago

It seems like not all my attachments got posted. Let me know if you would like them or if I should share my entire repo.

jjb169's avatar
jjb169
Icon for New Contributor rankNew Contributor
1 month ago

Hello,

Amazing, thank you so much!! I'll try following these steps next time I am at my workstation, as I am currently barred by lots of snow.

If you would be able to share your board model file, or just the entire repo as you offer for reference, that would be phenomenal. I am not deeply experienced with OFS, and much of this process is new to me, so I greatly appreciate your help.

Best,
James

  • jchecmu's avatar
    jchecmu
    Icon for New Contributor rankNew Contributor
    1 month ago

    The board model file is nothing more than the total FPGA resources (ALMs, FFs, DSPs, M20Ks, etc). You can read more about it here oneAPI Accelerator Support Package(ASP) Reference Manual - OFS and look at the existing ones for reference.

    I need some time to clean up the repo but will get to it when I can 

    For AGIB027R29A1E1VB, the resource counts are:

    <alms num="912800"/>

    <ffs num="3651200"/> <!-- 4xALMs, since there are 4 FFs per ALM. hyper-regs not counted -->

    <dsps num="8528"/><!-- 27-bit elements -->

    <rams num="13272"/><!-- M20Ks -->

    <mlabs num="45640"/> <!-- half of total labs (10 ALMs each) -->

     

    • jjb169's avatar
      jjb169
      Icon for New Contributor rankNew Contributor
      16 days ago

      Hello,

      Thank you for the clarification! Sorry for the delay, I've been running into crashes during compilation that I think are memory related, so I'm currently waiting on a delivery of 128GB RAM.

      On one run, however, I did encounter a compilation error as shown below, but I'm thinking it may be due to a mistake I made when modifying the mem_ss.ip as you listed in step 2.

      Error (17045): Input port I of I/O input buffer primitive local_mem_wrapper|mem_ss_top|mem_ss_inst|mem_ss|hps_emif|hps_emif|arch|arch_inst|bufs_inst|gen_rzqin.ibuf is not connected. It must be driven by a top-level pin. File: /home/jbick/OFS/OFS_BUILD_ROOT/ofs-agx7-pcie-attach-slim/work_iseries-dk_minimal_fim/ipss/mem/qip/mem_ss/mem_ss/mem_ss_mem_ss_200_rod65uq/synth/ip/mem_ss_mem_ss_200_rod65uq/mem_ss_mem_ss_200_rod65uq_emif_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv Line: 1138

      Error: Failed to synthesize partition 

      Once my RAM is delivered and installed, I will try the process once more and report the results!

      Thanks!
      James

      • jchecmu's avatar
        jchecmu
        Icon for New Contributor rankNew Contributor
        11 days ago

        Upon further testing, I found that my solution still has errors. Even though aocl diagnose passes, the default vector add program fails. I am trying to understand the issue before I share more. Thanks