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Björne2's avatar
Björne2
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2 years ago

Advice on CNN inference on Agilex 7 using oneAPI

Greetings everyone, I'm tasked with porting an CNN trained with PyTorch to an Agilex 7 FPGA using HLS. I think the right tool for the job is oneAPI. Since this is not a completely novel task, I wond...
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whitepau_altera's avatar
whitepau_altera
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2 years ago

The "Report has invalid data. Ok to proceed?" error is unrelated to the bandwidth notes you are seeing; this is a known defect in the reports that you may ignore.

The incorrect Global Memory Bandwidth estimates might be an issue with your BSP; does the board_spec.xml that you got from Terasic have any value specified for Global Memory Bandwidth?

Björne2's avatar
Björne2
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2 years ago

I think so. /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex/hardware/B2E2_8GBx4/board_spec.xml contains:

<!-- DDR4-2666 -->
<global_mem name="DDR" max_bandwidth="85312" interleaved_bytes="1024" config_addr="0x018">
    <interface name="board" port="kernel_mem0" type="slave" width="512" maxburst="16" address="0x00000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem1" type="slave" width="512" maxburst="16" address="0x200000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem2" type="slave" width="512" maxburst="16" address="0x400000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem3" type="slave" width="512" maxburst="16" address="0x600000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
</global_mem>

Moreover, if I compile an equivalent OpenCL kernel (aoc -bsp-flow=flat -rtl vector_add.cl) global memory bandwidth is estimated correctly (see screenshot).

  • whitepau_altera's avatar
    whitepau_altera
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    2 years ago

    Thanks Bjorne; I'll forward this to engineering, you may have found a report bug.

  • Björne2's avatar
    Björne2
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    2 years ago

    Hello again. I might have solved my problem. Apparently the -Xstarget option should name a specific board and not an FPGA family. So with -Xstarget=B2E2_8GBx4 the generated report looks much better. When synthesis is done in a few hours I'll check if I can run the generated bitstream on the FPGA.

  • Feng-Y-28's avatar
    Feng-Y-28
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    2 years ago

    Hi Bjorne

    May I get your environment set for DE10_Agilex?

    My issue was stuck for half a month without process.

    Could you give me the following enviro information, which can run the generated bitstream on the FPGA:

    • oneAPI DPC++ base toolkit version
    • Quartus Prime version

    I tried the 24.2 and 24.1 base toolkits, but all failed.

    Regards

    Feng