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Björne2's avatar
Björne2
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2 years ago

Advice on CNN inference on Agilex 7 using oneAPI

Greetings everyone, I'm tasked with porting an CNN trained with PyTorch to an Agilex 7 FPGA using HLS. I think the right tool for the job is oneAPI. Since this is not a completely novel task, I wond...
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whitepau_altera's avatar
whitepau_altera
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2 years ago

It looks like you have some mismatched tools installed. You don't need the FPGA SDK for OpenCL; here is what you need (from our homepage

  • oneAPI DPC++ base toolkit 2024.2
  • FPGA support Package 2024.2 (the FPGA compiler is no longer distributed with the base toolkit since 2024.2)
  • Quartus Prime 21.2 (with Agilex 7 Device support)
  • BSP for DE10-Agilex card

For best results, use one of the FPGA code samples, as those are the ones we regression test:

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/GettingStarted/fpga_compile

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/GettingStarted/fpga_template

Björne2's avatar
Björne2
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2 years ago

Thanks for your advice. With the FPGA support package I can now
compile SYCL code for FPGA targets. It seems aoc (from the FPGA
support package) uses the correct BSP:

$ aoc -list-boards
Board list:
  B1E1_8GBx4
     Board Package: /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex

  B2E2_8GBx4 (default)
     Board Package: /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex

  ...

I create a pre-synthesis report from the FGPA vector_add example like this:

$ icpx -v -fsycl -fintelfpga -Xshardware -Xstarget=Agilex7  -fsycl-link=early vector_add.cpp -o reportz

When I open the report it says "Report has invalid data. Ok to
proceed?" If I do so I get a report that is not quite right. In
particular, the global memory bandwidth estimates are wrong (see
screenshot). Is there something else I need to do? Like add something
to the icpx command to get it to use the right BSP?

  • whitepau_altera's avatar
    whitepau_altera
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    2 years ago

    The "Report has invalid data. Ok to proceed?" error is unrelated to the bandwidth notes you are seeing; this is a known defect in the reports that you may ignore.

    The incorrect Global Memory Bandwidth estimates might be an issue with your BSP; does the board_spec.xml that you got from Terasic have any value specified for Global Memory Bandwidth?

    • Björne2's avatar
      Björne2
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      2 years ago

      I think so. /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex/hardware/B2E2_8GBx4/board_spec.xml contains:

      <!-- DDR4-2666 -->
<global_mem name="DDR" max_bandwidth="85312" interleaved_bytes="1024" config_addr="0x018">
    <interface name="board" port="kernel_mem0" type="slave" width="512" maxburst="16" address="0x00000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem1" type="slave" width="512" maxburst="16" address="0x200000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem2" type="slave" width="512" maxburst="16" address="0x400000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
    <interface name="board" port="kernel_mem3" type="slave" width="512" maxburst="16" address="0x600000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
</global_mem>

      Moreover, if I compile an equivalent OpenCL kernel (aoc -bsp-flow=flat -rtl vector_add.cl) global memory bandwidth is estimated correctly (see screenshot).

      • whitepau_altera's avatar
        whitepau_altera
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        2 years ago

        Thanks Bjorne; I'll forward this to engineering, you may have found a report bug.