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Björne2's avatar
Björne2
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2 years ago

Advice on CNN inference on Agilex 7 using oneAPI

Greetings everyone, I'm tasked with porting an CNN trained with PyTorch to an Agilex 7 FPGA using HLS. I think the right tool for the job is oneAPI. Since this is not a completely novel task, I wond...
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whitepau_altera's avatar
whitepau_altera
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2 years ago

Do you have a board in mind? Keep in mind that if you wish to use oneAPI FPGA Acceleration, you should choose an acceleration card with a supported BSP. We have a list of vendor cards on our homepage:

https://cdrdv2.intel.com/v1/dl/getContent/824530

Instead of building a full oneAPI BSP, you can also use the oneAPI DPC++/C++ compiler to create IP that you can integrate using a platform designer system. We demonstrate this in the Platform Designer code sample, and the Nios V reference design. You can learn more about IP interface customization by studying the HLS Flow Interfaces code samples as well.

Manually integrating your IP with Platform Designer (or SystemVerilog/VHDL if you are so inclined) gives you the ability to accelerate the embedded HPS, so you are not tied to an x86-64 host CPU.

Björne2's avatar
Björne2
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2 years ago

> Do you have a board in mind? Keep in mind that if you wish to use
> oneAPI FPGA Acceleration, you should choose an acceleration card
> with a supported BSP. We have a list of vendor cards on our
> homepage:

Yeah, the board is a DE10 Agilex 7 from Terasic. The exact model is
AGF 7 014 B2E2_8GBx4.

> Instead of building a full oneAPI BSP, you can also use the oneAPI
> DPC++/C++ compiler to create IP that you can integrate using a
> platform designer system.

Well, I have a server license for Quartus Prime 21.2. Previously I
have used the aoc (Intel(R) FPGA SDK for OpenCL(TM) Kernel Compiler)
command to build FPGA bitstreams from OpenCL code so I think I already
have a suitable BSP installed. What I'm missing is how to "connect"
icpx (Intel(R) oneAPI DPC++/C++ Compiler) to the FPGA. It was easy
with OpenCL. I just compiled the kernel with aoc and then loaded it
onto the FPGA with OpenCL host code. It appears it is not that easy
with SYCL.

  • whitepau_altera's avatar
    whitepau_altera
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    2 years ago

    There is an additional step; with OpenCL (and indeed, earlier versions of oneAPI) we shipped some popular BSPs along with the tools, but since 2022 we stopped that to limit the installation size. You should be able to get a BSP from Terasic (indeed it should have been provided when you purchased it). Once you install the BSP, you can point the compiler to it when you compile your code. We explain how to do this in the code samples.

    Managing an FPGA Board

    FPGA Compile Code Sample

    FYI: that BSP depends on an older version of Quartus, and unless Terasic updates the BSP, it will fall out of the support window.

    • Björne2's avatar
      Björne2
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      2 years ago

      Thanks for the advice. Does the BSP have to be specific to SYCL or is
      a BSP for OpenCL sufficient? Anyway, I install OneAPI as described
      here:

      https://www.intel.com/content/www/us/en/developer/tools/oneapi/base-toolkit-download.html?operatingsystem=linux&linux-install-type=offline

      Then I source the ~/intel/oneapi/setvars.sh script to run SYCL tools
      and I create the Vector Add project. Compiling it for cpu-gpu works
      fine, but not when I compile it for FPGA targets:

      icpx -fsycl -fintelfpga -Xshardware -Xstarget=Agilex7 -v -Wsycl-strict vector-add-buffers.cpp

      I get the following error message:

      llvm-foreach --out-ext=aocx --in-file-list=/tmp/icpx-003d458ab4/vector-add-buffers-bc1783.txt --in-replace=/tmp/icpx-003d458ab4/vector-add-buffers-bc1783.txt --out-file-list=/tmp/icpx-003d458ab4/vector-add-buffers-1dc7d3.aocx --out-replace=/tmp/icpx-003d458ab4/vector-add-buffers-1dc7d3.aocx --out-increment=a.prj -- /vol/opt/intelFPGA_pro/21.2/hld/bin/aoc -o /tmp/icpx-003d458ab4/vector-add-buffers-1dc7d3.aocx /tmp/icpx-003d458ab4/vector-add-buffers-bc1783.txt -sycl -dep-files=/tmp/icpx-003d458ab4/vector-add-buffers-f000eb.d -output-report-folder=a.prj -g -hardware -target=Agilex7
AOCL_TMP_DIR directory was specified at /home/bjourne/.cache/aocl.
Ensure Linux and Windows compiles do not share the same directory as files may be incompatible.
InvalidModule: Invalid SPIR-V module: unsupported SPIR-V version number 'unknown (66560)'. Range of supported/known SPIR-V versions is 1.0 (65536) - 1.3 (66304)
Error: SPIRV to LLVM IR FAILED

      I'm using the Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline
      Compiler version 21.2.0. Perhaps there is some mismatch between what
      the OneAPI tools expects and what the offline compiler is capable of?