Forum Discussion
DongWang-BJTU
Occasional Contributor
Occasional ContributorPerformance difference between OpenCL 18.1 Std and Pro for FPGA ?
I was compiling the same kernel code by using both v18.1 std and pro. For the standard version, I could achieve a fmax around 220 MHz, but for pro version, the fmax is only 190 MHz. I further compar...
MuhammadAr_U_Intel
Contributor
ContributorHi,
Is there any specific example you are using for comparison ?
If the example is from OpenCL examples provided by Intel, I can try it out on my end.
Thanks,
Arslan
DongWang-BJTUOccasional Contributor
Occasional ContributorAnother odd thing is that sometimes 18.1 Pro generates unreasonable registers for private variables as follow:
The variable table_p2s_prefechtor is actually 16-bit width (unsigned short), but the compiler make it 512-bit wide, this makes feedback logics in-efficient.
For 18.1 std version, there is no problem:
