Forum Discussion
Hi ,
Would recommend to try out the code in v19.4 as mentioned in previous answer .
Please refer to the programming guide for some more clarification regarding recommended practices.
Please adhere to the statements in section
5.4.4. Restrictions in the Implementation of Intel FPGA SDK for OpenCL Channels Extension
like the one below.
"Performance of a kernel that has multiple accesses (reads or writes) to the same channel might be poor."
Also please refer to the following thread for some rules about multiple channel writes.
https://forums.intel.com/s/question/0D50P00003yyMFISA2/compiler-error-multiple-channel-write-sites
For implementing fence also please refer to
Please let us know , once you have rewritten the code following the guidelines.
Thanks and Regards
Anil