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MGRAV's avatar
MGRAV
Icon for New Contributor rankNew Contributor
5 years ago

n-bit intergers and memory broadcasting on FPGA using DPC++

Hi, I will start a new project of pattern search using FPGA. I need to have n-bit integer to store the pattern, and be able to broadcast the memory to do multiple pattern search in parallele with a...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi,

Im not familiar with DPC++ but since you are using Quartus, I suggest you to use either VHDL or Verilog, assuming you want to use IPs from Quartus in your design, e.g Fifo for memory store your pattern ---> can be generate to HDL (VHDL/Verilog).

Thanks,

Regards