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elias94
New Contributor
New Contributorlow occupancy of the DDR in HAN Pilot platform with opencl
I have a simple vectorized code with just 4 reads and 4 writes in the DDR with a clock frequency of 360 MHZ and i only achieve 10.6% occupancy for the read with a bandwidth of 612MB/s and the same f...
elias94New Contributor
New ContributorHi Adzim
No, it is not a Terasic design. I modified and used the vector_add design provided by intel (examples_aoc). The occupancy that i achieve with one 1 read and 1 write is 77%. But when i increase the reads and writes in parallel, (for example 2,4,8,16) my occupancy is always lower than 30%
