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Pan
New Contributor
New ContributorIntel HLS (19.4) - Not supported device family except Stratix 10
I always used Arria10 device, when compiling with 19.3 version and everything worked as expected. I shifted to 19.4 compiler recently, and since the shift, an error has been occurring when other dev...
Hi,
I am able to compile the example design in HLS compiler v19.3 and v19.4 and could not duplicate the error as shown on your side.
It seems like the problems is cause by the device files are not installed correctly.
Could you try to reinstall the Arria 10 device files?
Thanks
PanNew Contributor
New ContributorHi,
I will attach the compilation results of the last example I shared with you. When I looked into foo_generation.rpt, there is one difference at the start:
For 19.3 (solution_8):
Info: Starting: Create simulation model
Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo --family="Arria 10" --part=10AX115U1F45I1SGFor 19.4 (solution_9):
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo.ip --synthesis=VERILOG --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo --family="Stratix 10" --part=UnknownThe thing is - makefile is the same, code is the same, the enviroment set the same way and only compiler version is different. I don't know where foo_internal_inst comes from in case of 19.4. It just does. You will see 19.3 works with foo, not foo_internal_inst.
Thanks
