Hi,
I will attach the compilation results of the last example I shared with you. When I looked into foo_generation.rpt, there is one difference at the start:
For 19.3 (solution_8):
Info: Starting: Create simulation model
Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_8/intel_cosim.prj/components/foo/foo --family="Arria 10" --part=10AX115U1F45I1SG
For 19.4 (solution_9):
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo.ip --synthesis=VERILOG --output-directory=/home/local/xpanak04/p4base/compiler/p4hls/intel/tutorials/1_possible_cpp_structure/solution_9/intel_cosim.prj/components/foo/foo --family="Stratix 10" --part=Unknown
The thing is - makefile is the same, code is the same, the enviroment set the same way and only compiler version is different. I don't know where foo_internal_inst comes from in case of 19.4. It just does. You will see 19.3 works with foo, not foo_internal_inst.
Thanks
New Contributor
