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caron's avatar
caron
Icon for New Contributor rankNew Contributor
6 years ago

Intel FPGA SDK for OpenCL : how to generate an aocx file by the output of the OpenCL parser?

I want to modifying the Verilog code in the output of the OpenCL parser. Which is generated by the command "aoc -c -g device/vector_add.cl". And then I want to generate .aocx file from the folder. ...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago
Hello, You can do that, however, this might change the functionality of the design. Furthermore, it might bring some timing issues which will increase the design complexity. Thanks