Forum Discussion
caron
New Contributor
New ContributorIntel FPGA SDK for OpenCL : how to generate an aocx file by the output of the OpenCL parser?
I want to modifying the Verilog code in the output of the OpenCL parser. Which is generated by the command "aoc -c -g device/vector_add.cl". And then I want to generate .aocx file from the folder. ...
FawazJ_Altera
Frequent Contributor
Frequent ContributorHello,
You can do that, however, this might change the functionality of the design. Furthermore, it might bring some timing issues which will increase the design complexity.
Thanks
