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PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
5 years ago

In XILINX there is this DONT_TOUCH or KEEP attribute that will constraint the synthesis tool to not optimize the design and is wondering if there is something similar in Altera that we could use.

I am working on a project related to completion detection in asynchronous circuits and I have chosen the Altera FPGA as my test platform. The decision to use the Altera platform is that it is the mos...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Is there a reason to keep the design with schematic entry? You may convert the schematic to Verilog/VHDL file and use the keep/preserve in the HDL file.

Thanks.

Best regards,

KhaiY

  • PSriv8's avatar
    PSriv8
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi

    I have used schematic entry because I am not very comfortable with HDL language. However, I can convert the schematic entry into an HDL language. I have done that already, and now my question is how to use the keep/preserve in the HDL file. I am using the quartus lite version, can I use the keep/preserve or I need to use the paid version of Quartus prime software?