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PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
5 years ago

In XILINX there is this DONT_TOUCH or KEEP attribute that will constraint the synthesis tool to not optimize the design and is wondering if there is something similar in Altera that we could use.

I am working on a project related to completion detection in asynchronous circuits and I have chosen the Altera FPGA as my test platform. The decision to use the Altera platform is that it is the mos...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

In the Intel Quartus Prime software, you can use keep/preserve synthesis attribute in the HDL (VHDL attribute / Verilog attribute) but not in schematic. If you would like to preserve the register, you may do so by using the Assignment Editor - 'Preserve Registers'. This assignment prevents a register from minimizing away during synthesis and prevents sequential netlist optimization.

Thanks

Best regards,

KhaiY

PSriv8's avatar
PSriv8
Icon for New Contributor rankNew Contributor
5 years ago

Thank you for your reply KhaiY. Could you please assist me how can I keep/preserve synthesis attribute in the Verilog language? I am a beginner in FPGA and Quartus, and I am not familiar with the basics of using it. One more thing, when I follow the path Assignment-->Assignment Editor, I am not getting 'Preserve Registers' option. I have shared the screenshot of what I can see after selecting Assignment editor. I would be grateful if you can help me out.

I am using Quartus Prime Lite Edition.

Regards

Pallavi