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ArthurRatz's avatar
ArthurRatz
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6 years ago
Solved

I cannot build and run my code for Intel PAC platform in Intel DevCloud.

Hi Everyone,

For a few last days long, I'm no longer able to compile and run my code in Intel DevCloud for oneAPI projects.

The attempts to compile and run my code typically end up with the following error message:

I would kindly appreciate for any assistance. Please help me to solve this problem. My DevCloud account id is u39016.

Thanks in advance,

Arthur.

  • JananiC_Intel's avatar
    JananiC_Intel
    6 years ago

    Hi,

    Thanks for reaching out.

    You can compile and run the oneAPI samples on FPGA platform in Intel Devcloud.Kindly make sure you use the below commands to compile and run the samples.

    build_fpga_emu.sh

    source /opt/intel/inteloneapi/setvars.sh
make fpga_emu -f Makefile.fpga

    run_fpga_emu.sh

    make run_emu -f Makefile.fpga

    Try this and let us know the updates.


11 Replies

  • ArthurRatz's avatar
    ArthurRatz
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi, I'm using Intel DevCloud for Intel oneAPI projects. Previously I could compile and run my CL/SYCL program on Intel PAC Platform, but now I experience these difficulties. Also, as I've inspected the following issue, the quartus_fit process crashes when an amount of reserved virtual memory exceeds 16GiB ~ 16384 MB for this process.

    Looking forward for this issue resolution as soon as possible :)

    Arthur,

  • JananiC_Intel's avatar
    JananiC_Intel
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    6 years ago

    Hi,

    Thanks for reaching out.

    You can compile and run the oneAPI samples on FPGA platform in Intel Devcloud.Kindly make sure you use the below commands to compile and run the samples.

    build_fpga_emu.sh

    source /opt/intel/inteloneapi/setvars.sh
make fpga_emu -f Makefile.fpga

    run_fpga_emu.sh

    make run_emu -f Makefile.fpga

    Try this and let us know the updates.


  • ArthurRatz's avatar
    ArthurRatz
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    6 years ago

    Hi, JananiC_Intel

    Yes, exactly it works for me, *BUT* it does *NOT* work when compiling this code for Intel PAC card.

    Arthur,

  • ArthurRatz's avatar
    ArthurRatz
    Icon for New Contributor rankNew Contributor
    6 years ago

    Here's what I'm doing:

    source /opt/intel/inteloneapi/setvars.sh --force

    make run_hw -f Makefile.fpga

  • ArthurRatz's avatar
    ArthurRatz
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    6 years ago

    It normally compiles it with the following commands:

    dpcpp -O2 -g -std=c++17 -fintelfpga -c src/simple-add-usm.cpp -o a.o -DFPGA=1
    dpcpp -O2 -g -std=c++17 -fintelfpga a.o -o simple-add-usm.fpga -Xshardware

    2. Also, I've got a question for you if can I compile my code for Intel PAC card hardware offline (e.g. on-premises) without Intel PAC card installed ?

    Could you please guide me how to do that ?

    Arthur,

  • ArthurRatz's avatar
    ArthurRatz
    Icon for New Contributor rankNew Contributor
    6 years ago

    I'm sorry to inform you that this didn't work. First I've tried to compile of the samples for Intel PAC board and it finished compilation successfully, *BUT* when I tried to compile my project for Intel PAC hardware, the compilation ended up with the same error:

    Error (170143): Final fitting attempt was unsuccessful
    Error: An error occurred during routing
    Error: Quartus Prime Fitter was unsuccessful. 2 errors, 675 warnings
    Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
    Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
    Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
    Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
    Error: Compiler Error, not able to generate hardware

    clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
    Makefile:19: recipe for target 'fpga' failed
    make: *** [fpga] Error 1

    Looking forward to your reply and the following critical issue resolution.

    Arthur,

  • JananiC_Intel's avatar
    JananiC_Intel
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    6 years ago

    Hi,

    Thanks for the update.

    In Datacenter devcloud we have FPGA emulator and we do not have PAC in it.

    Could you let us know which devcloud are you using(Datacenter/FPGA)?

  • JananiC_Intel's avatar
    JananiC_Intel
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    As your issue is related to FPGA , we are moving your case to FPGA forum for quicker response.

    Thanks


    • Dr_FPGA's avatar
      Dr_FPGA
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi Janani,

      Now I am really confused. I thought this is THE FPGA FORUM for High Level Design. Please stop this practice of bouncing forum threads. Other users are interested in the solutions to the questions,

      Just my 2c worth.

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,


    May I know if you are able to share with me your source code so that I can debug it to see if it is related to the design not able to fit into the FPGA or due to the system memory issue?


  • Mickleman's avatar
    Mickleman
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I have the same problem. Have you found a solution yet Arthur? The solution suggested above by Janani only applies to the emulator.

    Marcus