how to improve fmax for S10 FPGA when using OpenCL

I am porting my OpenCL design from Arria-10 to Stratix-10 device. On A10 FPGA (1150 device), the best fmax was around 210MHz, however, on Stratix-10 FPGA (2800 device), the best fmax was around 250MHz. The improvement in Fmax was very limited. The same code was used here, and the resource utilization on S10 are 49%(logic), 25%(RAM block) and 3%(DSP).

In the report.html file, the Fmax estimated was around 480MHz.

I reported the critical path by using the Timing Analyzer and found that the critical path passes through a region of PLL blocks as follow:

Is this caused by the long routing path ? How could I identify the real cause of the low fmax problem ?