How can I port RTL module into oneAPI FPGA programming ?

Hi hareesh,

Sorry for late reply. I have solved the problem that I encountered. The real question thta I want to ask is that, is there a way to illustrate the implementation of Avalon-Stream interface under backpressure modules ? Although I have solved the problem, I am still confused about the Avalon-Stream interface specified by the Intel OpenCL SDK website.

I do read some examples about OpenCL SDK programming, one for simple combinational circuit and another one for a very complicated extern memory interaction example. The true is that, combinational is too simple but interacting with external memory is too much complicated. Is there a mid-point example that I can explore ?

Best,

Jiajun.

Hi Hareesh,

Did you get anything back from your colleagues ? I tried implemented a simple Avalon Stream interface based on the oneAPI documents and also the given example. I modified the original combinational logic example into a sequential version. However, I still lack some more details:

1. I dont konw the exact specification of the required Avalon-Stream interface for porting RTL into oneAPI environment. Is there any worked example or detailed illustration that I can check ?

2. I am able to get the simulation waveform using ModelSim, however, I cannot read the Machine Generated signals... Is there any more convinient way to debug my RTL module ?

3. To my understanding and based on the given documents from oneAPI websites, I wrote the RTL code for porting a simple vector add RTL module into oneAPI, which may not meet the requirements of Avalon Stream interface. The code and XML file are attached below.

`timescale 1 ps / 1 ps

module lib_rtl (
  input   clock,
  input   resetn,
  input   ivalid,
  input   iready,
  output  ovalid,
  output  oready,
  input   [31:0]  datain1,
  input   [31:0]  datain2,
  output  [31:0]  dataout);

  logic [31:0] dataout_buffer, dataout_reg;
  logic ovalid_reg, oready_reg;
  
  assign ovalid = ovalid_reg;
  assign oready = oready_reg;
  assign dataout = (oready_reg & !iready) ? dataout_buffer : dataout_reg;

  // assign  dataout = result;
  // clock, ivalid, iready, resetn are ignored

  always @(posedge clock) begin
    // reset or non-valid input
    // all the signals are default zero
    if(!resetn || !ivalid) begin
      dataout_reg <= 0;
      dataout_buffer <= 0;
      oready_reg <= 0;
      ovalid_reg <= 0;
    end
    else if (ivalid) begin
      ovalid_reg <= 1;
      oready_reg <= 1;
      dataout_reg <= datain1 + datain2;
    end
  end

  always@(*) begin
    $display("ivalid = %d iready = %d  dataout_reg = %d\n", ivalid, iready, dataout_reg);
    $display("datain1 = %d data2 = %d dataout %d\n", datain1, datain1, dataout);
  end

endmodule

<RTL_SPEC>
  <FUNCTION name="RtlByteswap" module="lib_rtl">
    <ATTRIBUTES>
      <IS_STALL_FREE value="yes"/>
      <IS_FIXED_LATENCY value="yes"/>
      <EXPECTED_LATENCY value="0"/>
      <CAPACITY value="0"/>
      <HAS_SIDE_EFFECTS value="no"/>
      <ALLOW_MERGING value="yes"/>
    </ATTRIBUTES>
    <INTERFACE>
      <AVALON port="clock" type="clock"/>
      <AVALON port="resetn" type="resetn"/>
      <AVALON port="ivalid" type="ivalid"/>
      <AVALON port="iready" type="iready"/>
      <AVALON port="ovalid" type="ovalid"/>
      <AVALON port="oready" type="oready"/>
      <INPUT  port="datain1" width="32"/>
      <INPUT  port="datain2" width="32"/>
      <OUTPUT port="dataout" width="32"/>
    </INTERFACE>
    <REQUIREMENTS>
      <FILE name="lib_rtl.v" />
    </REQUIREMENTS>
  </FUNCTION>
</RTL_SPEC>

I also read some materials from Intel OpenCL SDK for FPGA docs, there are some documents telling how to mix RTL and OpenCL together, but I am not sure whether they are accurate reference docs. Please give me more details for further exploration.

Thanks for your kind reply and help.

Best,

Jiajun.