New Contributor
ModeratorHi @thj,
Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
If I understand the situation correctly, there are a way that you can set in the quartus to specify to the compiler on which VHDL version to use.
Please do look into the settings in the quartus project under Assignments -> Settings -> Compiler Settings -> VHDL Input
You would be able to chose the inputs there, please do let us know if that helps to clarify your doubts.
Best Wishes
BB
New ContributorHello BB,
Thank you for your answer.
At command line, I can invoke the i++ compiler with the compile flag --quartus-compile. That invokes the quartus synthesis tools (quartus compiler) with the fitter. The outcome of the fitter is important for me to estimate the resource consumption properly.
What I did is indeed to start the quartus project manually and changing the VHDL input to the correct version. Then I start the synthesis flow again. Now I investigate if the output is meaningful, because the i++ compile flow is broken, and I fear the quartus compile flow (fitter) optimizes away a lot because of not connected signals in the resulting hardware design.
By the way, I have instantiated an HDL object as described in the Intel High Level Synthesis Compiler Pro Edition Reference Manual Chapter 11.4. The reason is to investigate the resource consumption between a version written in HLS compared to one written in VHDL and the effect of the maximum throughput I can get when I insatiate the HDL object within my component function. For me the C++ (HLS, DPC++) features are very interesting, because that enables template metaprogramming as well and could be quite useful to create powerful designs with a minimum of resource consumption on FPGA hardware, too.
Best Regards,
Thomas
