HLS support in Lite 19.1

Hi,

The following is the output from the command prompt:

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E:\intelFPGA_pro\19.4\hls\examples\image_downsample>i++ --quartus-compile --simulator none -march=Cyclone10GX bmp_tools.cpp main.cpp resize.cpp -o test-fpga -v

Target FPGA part name: 10CX220YF780I5G

Target FPGA family name: Cyclone10GX

Target FPGA speed grade: -5

Analyzing bmp_tools.cpp for hardware generation

Analyzing main.cpp for hardware generation

Analyzing resize.cpp for hardware generation

Optimizing component(s) and generating Verilog files

aocl-opt.exe takes CPU load of 25% for 2 hrs

How long will it take to generate??