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ybrstud's avatar
ybrstud
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6 years ago

HLS Main Optimizer Failed: The command line is too long

Hello everybody,

currently I am working on a project, where I want to use the HLS compiler to use my c++ code on the FPGA. To your information: FPGA is CycloneV, Quartus version is 18.1 lite. Every time I got the same error messages from the Compiler, see my attached file: "The command line is to long. HLS main optimizer failed." This error message appears after about 30 minutes of compilation.

The HLS compilation in general works, because I compiled a few projects before, but in my c++ Code I add nothing new, so in my opinion it is not possible that the Code gots an error. The compilation for a processor e.g. x86 works fine.

My command to start the HLS compilation is: i++ --quartus-compile --simulator none -march=CycloneV file.cpp -o test-fpga -v

Could anybody help me to solve this issue?

Thanks in Advance!

Best regards, ybrstud

10 Replies

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    Could you provide me the information as below:

    1. OS version
    2. HLS Compiler version
    3. Log file
    4. Design code file

    Thanks

  • ybrstud's avatar
    ybrstud
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    6 years ago

    Hi MeiYanL_Intel,

    thanks for your reply.

    See my following answers to your issues:

    1. Windows 10 Home v1909 x64 OS
    2. Intel HLS Compiler Version 18.1.0 Build 625
    3. see attachment, but there is nothing useful documented
    4. sorry I can not provide this to you, but I only include the "HLS/hls.h" and the "HLS/ac_int.h" libraries, nothing else.

    I hope you have an idea concerning my problem.

    Thank you, ybrstud

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    I had tried to use the command "i++ --quartus-compile --simulator none -march=CycloneV counter.cpp -o test-fpga -v" to compile the design example: counter.cpp. There is no error and it is compile successfully.

    If you could not share the design file here, you can try to email me for the design file. I will try to compile the provided design file and duplicate the error for further investigate.

    Thanks

  • ybrstud's avatar
    ybrstud
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    6 years ago

    Yes exactly. As I mentioned in my initial commit: "The HLS compilation in general works, because I compiled a few projects before." There I use the same command line as in the project which fails...

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    It might be the design code problem. Could you provide the design code for further investigate?

    Thanks

    • ybrstud's avatar
      ybrstud
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      6 years ago

      Hi,

      is it possbile to you to check where the issue in the commit below has its origin?

      Maybe it is the same problem, because in the examples there should be no design code error.

      Thanks and best regards

  • SParv4's avatar
    SParv4
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    6 years ago

    Hi,

    HLS gets stuck at this same point with 19.1 Standard with the 'image_downsample' example.

    *******************************************************

    i++ debug log file

    This file contains diagnostic information. Any errors

    or unexpected behavior encountered when running i++

    should be reported as bugs. Thank you.

    *******************************************************

    Compiler Command: i++ -march=Arria10 bmp_tools.cpp main.cpp resize.cpp -o test-fpga.exe

    • Engineer87's avatar
      Engineer87
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      2 years ago
      Hello. Arria10 chip design needs huge amount of Ram and pagefile. Even Bigger than 64 Gb. Thnks.
  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    I am using HLS Compiler Standard v19.1 in Linux version. There is two command methods I had tried to compile the design file, could you try the command as below:

    1. make test-fpga
    2. i++ -march=Arria10 bmp_tools.cpp main.cpp resize.cpp -o test-fpga

    By using these two command, I am able to compile the design successfully.

    May I know the OS,Kernel and GCC version you are using?

    Thanks

  • Engineer87's avatar
    Engineer87
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    2 years ago
    Hello i finally found the solution. The answer is : compiling c++ code in fpga mode with i++ compiler needs a huge amount of Ram and hdd resource for page filing. For example a cycloneV design needs about 64gb ram and resource. it depends on your design. Make a huge pagefile in OS and bring a huge ram. That is it. Thanks.