New Contributor
Occasional Contributorcan u attach debug.log generated after running the command??
if u want to compile quartus project, u can use quartus gui software to open and synthesize ur generated proj. From the GUI, it can provide more information.
New ContributorThanks for your advice.
There is only one line of command in debug.log, and then there is no other information.
I only know using Quartus HLS compiler to do high level synthesis. How to use Quartus GUI to do HLS?
I use Quartus Prime Lite 18.1 to connect IP and design system, but I don't know it can synthesis IP.
Are there any related tutorials or guide documents?
Thanks!
Occasional ContributorI am also trying hls but 19.1 version since 2wk ago. at first, i tried with linux but thing did not go well. so im running it on window now. It can run smoother. after having right experience, i ll move back to linux later. i suggest u to try a non-lite version on a virtual machine, get 30 day trial license to get it through, go through intel hls examples first, read the manual carefully.
Here something u can try now.
- check if hls support CycloneV or not
- try hls with Arria10 (all hls versions support arria10)
- run the following command
# --debug-log -v -ghdl --> turn on all logging feature i++ hello.cc -v -march=Arria10 --debug-log -v -ghdl --simulator none -o test-fpga # should see a new folder test-fpga.proj. inside it, there are subfolders: components, quartus, reports, verification # synthesize component with quartus i++ hello.cc -v -march=Arria10 --debug-log -v -ghdl --quartus-compile # or u can use quartus to open project <ur project folder>\test-fpga.proj\quartus\quartus_compile.qsf
Frequent ContributorThe crash here is happening in the C to RTL conversion step and hence, there is not RTL project to put into Quartus. The optimizer FAILED error typically happens when your design is too complex or not FPGA-friendly, and the compiler fails to generate RTL from it. There is generally no way of debugging this issue. The only remedy is to start small and compile your code step by step and add more components to it as you go to see when the crash happens, or redo your design completely and write it in a more FPGA-friendly manner.
