Hello, how can dataflow parallelism be implemented in Intel HLS in the STD edition without using the task mechanism (only available in the PRO edition)? A typical use case is shown here: https://youtu.be/aH1O4DZnjf8 Thanks, Thomas

>I would like to suggest to used parallelize loops in Quartus Prime Standard Intel HLS to increase the parallel dataflow.

Loop parallelization (i.e. unrolling) is completely different from dataflow parallelization. The former is for parallelizing iterations within one loop, the latter is for parallelizing multiple separate loop bodies with respect to each other; you cannot achieve the latter using the former. I am astonished that Intel is limiting certain features of the HLS compiler to the PRO version, preventing people who use older FPGAs only supported by the Standard version from being able to access them.