FPGA reconfiguration for OpenCL logic

Please check the discussion in this thread:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-OpenCL-handles-multiple-accelerators-on-FPGA/td-p/30352

You can have multiple kernels/IPs in one .cl file, which will turn into one bitstream, and you can run the kernels in parallel by using multiple OpenCL queues without needing dynamic reconfiguration. The FPGA area will be shared between the different kernels/IPs in this case. Alternatively, you can also have multiple IPs in different .cl files to avoid sharing of FPGA area, synthesize each .cl file separately, and load all of the bitstreams at run time. Whenever a kernel associated with a specific bitstream is called, the OpenCL run-time will automatically reconfigure the FPGA with the associated bitstream.