DSP builder compilation error

Hello community,

I'm using the DSP builder to design the behaviour of my logic which shall be converted to VHDL to use it on my Cyclone IV FPGA board.

I want to use some LUTs and I have a strange behaviour depending on the values of the initialization array (Output value map).

If I initialize it with zeros (neither zeros(10,1) nor zeros(1,10) does work) I get an error while compiling the design:

Error reported by S-function 'mip_control' in 'project_name/Control':

DSP Builder for Intel(R) FPGAs - Advanced Blockset Internal Restriction: 'latency >= 0' in folder::internal::LatencyServicesImpl::getLatency at p4/ip/aion/src/alu_folder/latency_services.cpp:165.

If I initialize it with random numbers (both rand(10,1) and rand(1,10)) it works totally fine. --> resulting latency 3, 93 LUTs, no multipliers or memory bits.

Do you have any ideas or hints what to check or to modify? I've already lost a few days in my master thesis because of that problem :(.

Thanks a lot for any support in advance.

Tobias

I'm using DSP builder for MATLAB2019a and MATLAB2019a

Cyclone IV: EP4CE40F23C6

120MHz clock

0.08 MHz sample rate

no constrain latency

and I have already created some working VHDL files (without LUTs)