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Ghe0rghe's avatar
Ghe0rghe
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5 years ago
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Downsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset

Hello all, I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
  • SengKok_L_Intel's avatar
    5 years ago

    Hi,


    You may need a dual clock FIFO to transfer data between two different clock domains.


    Regards -SK