Forum Discussion

MAlek2's avatar
MAlek2
Icon for New Contributor rankNew Contributor
6 years ago

Division in HLS doesn't work

I'm trying to write a simple matrix inversion program and the generate an HDL code from it. I'm working with fixed point math. Here is a part of my code: typedef ac_fixed<40, 20, true> fixed_40_2...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

What is the exact error message? Could you share the full error message?

Thanks

MAlek2's avatar
MAlek2
Icon for New Contributor rankNew Contributor
6 years ago

Here is the full message from the compilator:

make -k target-fpga-nosim 
time i++ test1.cpp -march="Cyclone10GX" -v --time time_fpga.out -ghdl --simulator none --clock 200MHz -o target-fpga-nosim
Target FPGA part name:   10CX220YF780I5G
Target FPGA family name: Cyclone10GX
Target FPGA speed grade: -5
Analyzing test1.cpp for hardware generation
Optimizing component(s) and generating Verilog files
Compiler Error: The estimation for the area taken by this design far exceeds the size of the board.
Compiler Error: If you wish to continue compilation anyways, use the flag "--dont-error-if-large-area-est".
HLS Verilog code generation, llc FAILED.
Command exited with non-zero status 1
27.54user 0.40system 0:31.79elapsed 87%CPU (0avgtext+0avgdata 343632maxresident)k
Makefile:26: recipe for target 'target-fpga-nosim' failed
288912inputs+75928outputs (1158major+150067minor)pagefaults 0swaps
make: *** [target-fpga-nosim] Error 1
"make -k target-fpga-nosim" terminated with exit code 2. Build might be incomplete.