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HRZ's avatar
HRZ
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6 years ago
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Disable Hyperflex Optimization in OpenCL Compiler v18.1.2

How can I disable the Hyperflex optimization that is performed automatically by the OpenCL compiler on Stratix 10 in the v18.1.2 of the compiler? The v19.x versions of the compiler add the -hyper-optimized-handshaking option to disable this optimization; however, this option is not available on v18.1.2. Since my board's BSP is compatible with v18.1.2, I have to use that version. The Hyperflex optimization is impractical in my design due to its HUGE area overhead: 20% extra logic, 30% extra Block RAM compared to version with hyperflex optimization forcibly disabled by inferring burst non-aligned memory ports instead of aligned. I obviously want to use the version of my design with aligned memory ports due to higher memory performance and lower area overhead.

9 Replies

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/rn/archives/rn-hls-19-1.pdf shows the new feature for Hyper-Optimized Handshaking for Intel Stratix® 10 designs in OpenCL 19.1.

    This feature is not supported in OpenCL 18.1.2.

    I found there is an BSP for Stratix 10 as link below:

    http://fpgasoftware.intel.com/opencl/19.1/?edition=pro&download_manager=dlm3

    Also, I will need to do a test for OpenCL compiler 19.1 version and Quartus Prime Pro 18.1.2 version. If I done the test, I will tell here.

    Thanks

    • HRZ's avatar
      HRZ
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      6 years ago

      @MeiYanL_Intel​ That is not true, the HyperFlex optimization already existed in v18.1.x (and maybe even before that); it just had a slightly different name. Please check the attached screenshot from the HTML report of a test compilation using Quartus v18.1.2 against the s10_ref BSP:

      Also regarding the link to the BSPs you posted: those BSPs are for Intel's reference boards. I am not using an Intel reference board. I am preparing my environment for the OpenCL BSP of the PAC S10 board which is supposedly going to be released to public soon as part of Intel Acceleration Stack Version 2.0, and will be compatible with Quartus v18.1.2. It is very interesting that even Intel seems to have a hard time keeping OpenCL BSPs for their non-reference boards up-to-date with latest versions of the compiler; Qurtus v18.1.2 was released over 6 months ago and there have been three major releases of Quartus since then...

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    I am understand with the situation with you.

    For the feature to disable Hyperflex Optimization was released from Quartus Prime Pro v19.1.

    For you information, the Acceleration Stack 2.0.1 version will be release soon and supported in Quartus Prime Pro 19.2 with BSP provided.

    Thanks

    • HRZ's avatar
      HRZ
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      6 years ago

      >For you information, the Acceleration Stack 2.0.1 version will be release soon and supported in Quartus Prime Pro 19.2 with BSP provided.

      I guess that is better than nothing. Can you elaborate if this version is expected to be released before the end of this year? Also, will this version be available to public or will it require signing an NDA just like the current Acceleration Stack 2.0?

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    6 years ago

    Hi,

    Since we have released acceleration stack v2.0, the accelearation stack v2.0.1 will be release within few week later based on the schedule.

    For the second question "will this version be available to public or will it require signing an NDA just like the current Acceleration Stack 2.0?" , I have to check it internally. Also, you can contact local FAE for more information about this.

    Thanks

    • HRZ's avatar
      HRZ
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      6 years ago

      I would appreciate any info you could provide on this topic.

    • HRZ's avatar
      HRZ
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      6 years ago

      Finally some good news! Time to take the BSP out for a spin. 😉