New Contributor
New Contributorhttps://github.com/d3x0r/JTAG_Interface/blob/stable_2Ghz/FPGA/projects/example_simple/clock-module.v
This ticks the counter at 300-600ps. Depends on temperature. Uses a synthetic clock (internal not gate driving a divide by 2 wire). I also can't remove or change anything, or it stops behaving so well. All the other parts must space out the clock from the counter enough that it work (or maybe the clock parts itself?)
But, if I put my finger on it (warm it up) it goes slower... if I blow on it I can get it down to 400ps pretty regularly.
This is a discontinued board though, so it's probably not the best choice anyway which is sad. It also appears that the board didn't actually expose any header pins to the FPGA - though I guess the pci-e slot is attached to the FPGA, so I'd need to get a socket and hook into that in order to give a hardware signal to this.
The counter also resets at 40 bits instead of counting all 64 bits. which is a little odd - but would be fine that's like 512 seconds, and I could manually count the upper bits when that wraps - it's a little strange, since I started the design with 40 bits for the clocks anyway - ended up extending the counters to 64 just because it was easier to wire two 32 bit values to the ports.
I know what I see can't be seen by you, but it's not just running on a simulator, it's physically running here on my desk and clocking at that rate - so I don't understand why I should be convinced that what is happening isn't happening, and can't be done.
Frequent Contributor"This ticks the counter at 300-600ps. Depends on temperature. "
"But, if I put my finger on it (warm it up) it goes slower... if I blow on it I can get it down to 400ps pretty regularly."
" I also can't remove or change anything, or it stops behaving so well. "
"Uses a synthetic clock (internal not gate driving a divide by 2 wire). "
So you are using a feedback loop of gates to generate am oscillator, which is not very stable nor reproducible.
We have told you that multiple times that this is an unreliable design approach.
That is why we have fixed clock sources and PLL blocks to be able to generate fixed frequency stable clock sources.
IDK what is the utility of a 'stopwatch' is where the clock wanders all over the place based on temperature.
"I know what I see can't be seen by you, but it's not just running on a simulator, it's physically running here on my desk and clocking at that rate - so I don't understand why I should be convinced that what is happening isn't happening, and can't be done."
I believe you were able to kludge together a one off hack. But you can't change it nor predict its frequency. Congratulations.
I'm done here. You don't want to listen to experienced FPGA designers that your approach is flawed. Good luck to you.
