New Contributor
Frequent ContributorUntil you can show the timing constraints and analysis 'Synthesizes just fine' is pretty meaningless when running the design on real hardware.
The FPGA simulation tools are infinitely fast and zero delay.
Real FPGA hardware is not.
It has nonzero setup and hold times on registers, and there are non-zero signal routing delays.
You need to provide info on how you are specifying and constraining your designs clocks (in the .sdc and .qsf files).
And the final placement and routing timing report should indicate that all timing constraints were met (or not)
and what the estimated maximum clock frequency is predicted to be.
Until you can provide that validation, loading a design into real hardware is a crap shoot if it works or not.
Just getting it thru synthesis, place, and route, but with no timing constraints, is meaningless.
New ContributorI got it to nearly a working state by removing a bunch of inferred latches; at least the initial state has 0's.
These are the unconstrained clocks. they are all outside of the counter. The last iCLK isn't mine, but is at the top of the main module
module MKRVIDOR4000_top ( // system signals input iCLK, input iRESETn,
And that top module I haven't touched.
I renamed my click to iCLK_ff, and it's not listed as a clock.
The other two bits are outputs from the jtag interface - they go to 'or' gates that should be the input latch signal, and the trigger from USB through jtag... they're not clocks either. I searched for how to fix some of these clock signals, and some said I could use Assignment Editor - but none of those show up in the assignment editor to make not clock.
I did try to define a clock for iCLK_ff,l but then it said there was a defined clock, and no reference to it.
create_clock -name {MyDesign:MyDesign_inst|COUNTER:inst6|iCLK_ff} -period 0.2 -waveform { 0 0.1 }
But even then, I can just put in arbitrary numbers - doesn't mean it would work any better.
https://github.com/d3x0r/STFRPhysics/blob/master/hardware/fpga/clock-module.4.v This is the version that is almost working. without any inferred latches.
