Developing a high speed stopwatch

Until you can show the timing constraints and analysis 'Synthesizes just fine' is pretty meaningless when running the design on real hardware.

The FPGA simulation tools are infinitely fast and zero delay.
Real FPGA hardware is not.
It has nonzero setup and hold times on registers, and there are non-zero signal routing delays.

You need to provide info on how you are specifying and constraining your designs clocks (in the .sdc and .qsf files).
And the final placement and routing timing report should indicate that all timing constraints were met (or not)
and what the estimated maximum clock frequency is predicted to be.

Until you can provide that validation, loading a design into real hardware is a crap shoot if it works or not.
Just getting it thru synthesis, place, and route, but with no timing constraints, is meaningless.