New Contributor
Frequent ContributorI decided to look thru your code and found it is not even close to synthesizable verilog.
I'm not even sure any simulator would handle it really well.
Generating a clock like this is just not going to work.
Do you use any timing constraints at all? If you did they likely all failed miserably.
You need to go back to the basics and understand what is and is not synthesizable verilog.
And #N delay parameter are ignored during synthesis in Quartus.
... always // Start at time 0 and repeat the begin/end forever begin iCLK <= !iCLK; end ... always @(posedge iCLK) begin clrA_ <= rstA; rCOUNTERa <= rCOUNTERa+1+(rstA_ ^ rstA)*256; end
So have you looked at the tutorials in ...
https://docs.arduino.cc/hardware/mkr-vidor-4000
On github this would be a good top level starting point ...
New ContributorSynthesizes just fine.
None of that mentions how to 'apply timing constraints'.
That link is just the link of the counter sources (and simulation param sources)... but repo and branch that has the complete Quartus and Arduino IDE sources. (sort of, need to install JTAG_interface lib separately so the Arduino uses a different place than this for the FPGA_bitstream.h) but still the resulting MKRVIDOR4000.ttf gets byte reversed and copied to that other place... and it's really just the FPGA part that we're talking about here, it downloads fine... the jtag interface it uses to communicate also works fine. I've added all sorts of things like 'debug' which is commented out now, but exposed various internal flags that could be seen by the main chip on the arduino.
https://github.com/d3x0r/JTAG_Interface/tree/d3x0r-hispeed-counter
clock-module.v lives here also...
https://github.com/d3x0r/JTAG_Interface/tree/d3x0r-hispeed-counter/FPGA/projects/example_simple
Looks like synthesis works to me...
I've tried to get simulation in Quartus to work - but examples use simulators that aren't an option anymore... and there's a lot of options I could pick that I don't know if they are all compatible, or what differences between the options are. So I've been using the simulator in Vivado....
This is first few latching level changes... this only uses the SimulationParams.v and clock.v (filled with various versions - this is actually the clock-module.v source) from the other repo's directory...
Single tick zoom level at first latch
I did stack a few nots together ...
always // Start at time 0 and repeat the begin/end forever
begin
//#1
iCLK <= !iCLK;
if( !iCLK ) begin
iCLKb <= !iCLKb;
if( !iCLKb ) begin
iCLKc <= !iCLKc;
if( !iCLKc )
iCLKd <= !iCLKd;
end
end
end
