DevCloud: Cannot compile Stratix 10 kernel (Tcl error)

Hi. Thank you for your efforts.

As stated in the last paragraph of my post, I basically don't know anything about TCL scripts besides what is said in the error message. I don't know how they work (thus neither how to edit them), and I don't even know where they are located. I am assuming I am using some kind of "default script" for the Quartus/OpenCL installation in DevCloud.

If you can point me to the location in the DevCloud system of that "default script", I will be able to share it with you. Nevertheless, it should not differ from everybody else's script.

Hello again.

Upon further inspection, this error also applies to the compilation of OpenCL kernels for Arria 10 devices, not only Stratix 10.

This is the compilation script for the Stratix 10 kernel:

#/bin/bash

source /glob/development-tools/versions/fpgasupportstack/d5005/2.0.1/inteldevstack/init_env.sh
source /glob/development-tools/versions/fpgasupportstack/d5005/2.0.1/inteldevstack/hld/init_opencl.sh
export FPGA_BBB_CCI_src=/usr/local/intel-fpga-bbb
export PATH=/glob/intel-python/python2/bin:${PATH}

aoc -v -report -board-package=/opt/intel/oneapi/intel_s10sx_pac mykernel.cl -o mykernel.aocx

This is the compilation script for the Arria 10 kernel:

#/bin/bash

source /glob/development-tools/versions/fpgasupportstack/a10/1.2.1/inteldevstack/init_env.sh
source /glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/init_opencl.sh
export FPGA_BBB_CCI_src=/usr/local/intel-fpga-bbb
export PATH=/glob/intel-python/python2/bin:${PATH}

aoc -v -report -board-package=/opt/intel/oneapi/intel_a10gx_pac mykernel.cl -o mykernel.aocx

Both scripts were made based on the corresponding documentation on this page: https://devcloud.intel.com/oneapi/documentation/job-submission/

Here's the error for a Stratix 10 compilation:

aoc: First stage compilation completed successfully.
Compiling for FPGA. This process may take a long time, please be patient.
Error (16556): The synthesis RTL for ip/ddr_board/ddr_board_acl_memory_bank_divider_1.ip has not been generated. Generate the synthesis RTL from within Platform Designer.
Error: Flow failed:
Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 357 warnings
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings

Here's the error for an Arria 10 compilation:

aoc: First stage compilation completed successfully.
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the Intel FPGA SDK for OpenCL Best Practices Guide for information on performance tuning applications for FPGAs.
Error (19273): Family Stratix 10 is not installed
Error: Flow failed: ERROR: Current design not found
Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 1 warning
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings

(Notice how the Arria 10 error references the "Family Stratix 10", although the specified BSP for compilation was /opt/intel/oneapi/intel_a10gx_pac).

Both errors reference the TCL scripts compile_script.tcl and build/entry.tcl, used automatically by the Quartus compiler. However, I don't know which is the absolute path to those scripts, so I cannot share them with you. If someone provides me with the absolute path to them, I will be able to share them here.