DevCloud: AOC Unable to compile kernels for device for any of the FPGA nodes: instantiates undefined entity "board" (reopened issue in new forum)

Hi,

I am checking this issues internally.

I will need some time and I will get back to you.

Thanks

Hi,

According to https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/acceleration-card-arria-10-gx/getting-started.html, the Intel PAC with Arria10GX FPGA is only used in Quartus Prime Pro v17.1.1. For OpenCL SDK only can 2 versions higher than Quartus Prime pro version as stated in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_getting_started.pdf in Chpater 3.5.1.

Also, I would like to confirm which device you are using, are you using Intel PAC with Arria 10GX FPGA or using Intel Arria 10GX?

Thanks

I am using the Intel FPGA DevCloud. So I'm using whatever is in the FPGA queue (batch@v-qsvr-fpga, nodes s001-n[137-139] and s001-n189). When given access I was instructed to provide beta feedback to Intel about their resource via the forums. The posts you link suggest that Intel has their own DevCloud configured in a way that prevent it from compiling OpenCL kernels.

This is the same feedback you gave in https://forums.intel.com/s/question/0D50P00004UAnXVSA1/how-to-use-paca10-with-intel-fpga-sdk-for-opencl-192, which is fine if a user has configured their own box with the wrong software versions, but again, this is Intel's machine. I did not configure it, I did not buy the parts, I do not have sudo. I am trying to escalate so that the admins in charge of it can fix the issue.

I am unclear on the distinction between those two devices, but here is the output of aoc -list-boards and aocl diagnose if that helps you determine which are in the Intel FPGA DevCloud nodes.

<userid>@s001-n137:~$ aoc -list-boards

Board list:

pac_a10

Board Package: /opt/a10/intelrtestack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp

<userid>@s001-n137:~$ aocl diagnose

--------------------------------------------------------------------

Device Name:

acl0

Package Pat:

/opt/a10/intelrtestack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp

Vendor: Intel Corp

Physical Dev Name Status Information

pac_a10_ec00001 Uninitialized OpenCL BSP not loaded. Must load BSP using command:

'aocl program <device_name> <aocx_file>'

before running OpenCL programs using this device

DIAGNOSTIC_PASSED

--------------------------------------------------------------------

--------------------------------------------------------------------

Device Name:

acl1

Package Pat:

/opt/a10/intelrtestack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp

Vendor: Intel Corp

Physical Dev Name Status Information

pac_a10_ec00000 Uninitialized OpenCL BSP not loaded. Must load BSP using command:

'aocl program <device_name> <aocx_file>'

before running OpenCL programs using this device

DIAGNOSTIC_PASSED

--------------------------------------------------------------------

--------------------------------------------------------------------

Device Name:

acl2

Package Pat:

/opt/a10/intelrtestack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp

Vendor: Intel Corp

Physical Dev Name Status Information

pac_a10_ec00002 Passed PAC Arria 10 Platform (pac_a10_ec00002)

PCIe 175:00.0

FPGA temperature = 48 degrees C.

DIAGNOSTIC_PASSED

--------------------------------------------------------------------

Call "aocl diagnose <device-names>" to run diagnose for specified devices

Call "aocl diagnose all" to run diagnose for all devices

<userid>@s001-n137:~$

Hi,

From the command here: https://software.intel.com/en-us/forums/intel-devcloud/topic/832012, I saw that you might be using Quartus/BSP and OpenCL SDK with 19.3 version.

Since the Intel PAC with A10GX FPGA need to be used BSP with version 17.1.1 and the OpenCL SDK version should be used as the same with BSP version or can only two version higher than BSP version.

Can you try to used BSP and OpenCL SDK with 17.1.1 version?

Thanks

In that thread I have documented trying all three (18.1, 19.2, 19.3) versions available on the Intel FPGA Cloud Beta. As stated before, I cannot reconfigure the machine, it's Intel's. One would expect your resources to have the necessary toolkits installed to use your own hardware in your own system.

We have reached out directly to our contacts at Intel and they've notified us they've contacted the cloud provider in charge of the Intel FPGA DevCloud and have asked that the appropriate toolkits be installed. But this is on the queue with other sysadmin requests and will take some time. Will follow-up after Thanksgiving

Hi,

I am understand your situation and I am checking internally and had reported these issues to the concern team.

I will reply here once I get reply from the concern team.

Thanks

Hi,

I am setting up the Devcloud and will test it on my side. Since I am still have to wait for the access for node s001-n137 to n139, I will try to test in other FPGA node with aoc command.

Thanks

Hi,

I would like to know which example you have compile?

I have try to compile on my side with other FPGA node for FPGA emulator and hardware with the command as below:

ssh decloud

git clone https://github.com/intel/BaseKit-code-samples.git

qsub -I -l nodes=1:fpga:ppn=2 -d .

cd BaseKit-code-samples/DPC++Compiler/vector-add/

vi build_fpga_emu.sh

#!/bin/bash

source /opt/intel/inteloneapi/setvars.sh

make fpga_emu -f Makefile.fpga

vi run_fpga_emu.sh

#!/bin/bash

source /opt/intel/inteloneapi/setvars.sh

make run_emu -f Makefile.fpga

vi build_fpga_hw.sh

#!/bin/bash

source /opt/intel/inteloneapi/setvars.sh

make hw -f Makefile.fpga

vi run_fpga_hw.sh

#!/bin/bash

source /opt/intel/inteloneapi/setvars.sh

make run_hw -f Makefile.fpga

qsub -I -l nodes=1:fpga:ppn=2 -d . build_fpga_emu.sh

qsub -I -l nodes=1:fpga:ppn=2 -d . run_fpga_emu.sh

qsub -I -l nodes=1:fpga:ppn=2 -d . build_fpga_hw.sh

qsub -I -l nodes=1:fpga:ppn=2 -d . run_fpga_hw.sh

You can have the output file by type the command cat run.sh.oXXXX.

Thanks

Mylee,

I am just returning from vacation, haven't gotten to try anything on the non-FPGA-queue nodes.

As the previous thread shows (before I was moved to this forum), I am trying a canonical OpenCL VectorAdd like follows:

__kernel void vectorAdd(__global float *A, __global float *B, __global float *C, int nelem) {
        int tid = get_global_id(0);
        if (tid < nelem) C[tid] = A[tid] + B[tid];
}

The end goal is the 27 kernels in https://github.com/vetter/shoc/tree/master/src/opencl/level2/s3d

The examples you show are DPC++ which is a superset of SyCL, there are not OpenCL kernels in that repository. I am not sure if the DPC++ stack even uses AOC and all the old Altera stuff like the OpenCL stack does, so I am not sure how they're relevant. Our client has expressed that they want OpenCL, not SyCL, much less a vendor superset of it.

Hi,

I would like to know which sample/example code you had used to do the compilation that make this error occured?

This is because I will try at one my side also.

Thanks