Create call signals in Platform Designer to run IP block

Hi,

"Are these signals generated just for the testbench or are they needed for communication between IP blocks ", the signals generated to use for connection between IP block. After you have done the system connecttion in platform designer, you can be generated verilog code and run in Quartus. The generated HDL for component can also run in an RTL simulator.

For easily connects components in an Intel FPGA tom simplify system design , the HLS compiler will generate standard interface design for interoperability like avalon-mm, avalon-st and other interface.

All scalar arguments results in an input conduit while all pointer/reference arguments becomes address input.

"Is there an existing example how to generate an IP block in HLS, implement it in Platform Designer and run it on a FPGA", this can be done after use the HLS compiler compile the c code and then implement in platform designer as in chapter 8.2 with link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf

Thanks