Component Done signal remains asserted in FPGA, not in Simulation

Hello,

I have created a component in HLS which should take a 1280 bit signal (passed by value), and should stream it out in 20 packets of 64-bit each.

The task is simple, and both the simulation and co-simulation in Modelsim work fine.

However, when I integrate this component in my design, I have observed with signalTap that the done signal once asserted for the first time it remains high, it does not go back to 0 after one clock cycle and the component hangs, being impossible to start it again as soon as new input data becomes available.

I have also realized, that if I stream out 3 packets or less, the signal gets properly de-asserted after one clock cycle as I would expect, and the component does not hang.

This is the code I have used:

void component algorithm_1((ac_int<1280> in,  ihc::stream_out<ac_int<64,false>,
                        ihc::firstSymbolInHighOrderBits<false>> &out_stream))
{
  ac_int<64> result = 0;

  for (char i = 0; i<20; i++)
    {
      result = (in >> 64*i) & 0xFFFFFFFFFFFFFFFF ;
      out_stream.write(result);
    }
}

What could be the reason why the Done signal remains asserted? I have checked the internals of the component, but I have not found any FIFO overflow on the IOWR

Thanks for your help