Forum Discussion
KennyT_altera
Super Contributor
6 years agoI just compile your design in normal compilation and DSE compilation in Q19.3
Both was without any error. This might be your individual computer issue?
- SAbde76 years ago
Occasional Contributor
Like I mentioned before, a colleague of mine is using the computer and compiling without problems. After experimentation I now suspect that the stratix V hard IP for PCIE is causing the issue. The error message does not appear if that module is not included in the project.